Dividers are frequently used in Phase Locked Loops (PLLs). In an approach, a sigma-delta modulator modulates dividers for fractional PLLs, i.e., PLLs that use a fractional value divider. Various dividers receive the clock signal from a Voltage-Controlled Oscillator (VCO) and count the clock pulses with various divider numbers at the same time. The sigma-delta modulator generates a new divider number whenever the current divider finishes counting. The new divider, e.g., through a multiplexer (MUX), selects the appropriate divider output to the phase detector. Because of the many dividers that operate at very high speeds at the same time, this approach generally consumes a significant amount of the power and layout area in a semiconductor chip in comparison with other components. Furthermore, since the various dividers have different divider numbers, the outputs of these dividers are asynchronous. As a result, when a number is selected through the MUX, glitches are easily generated and thus degrade the capabilities of the PLL.
In another approach, there is one divider for the PLL. Here, the sigma-delta modulator generates a new divider number whenever the divider finishes the current counting cycle. The divider then loads this new number into its corresponding counter before performing the next counting cycle. The divider, however, cannot miss any clock pulse from the VCO. For example, if the divider counts each clock pulse at the rising of the clock, the divider must load the new divider number before the falling edge of the clock. This approach does not work well at very high speeds, e.g., above 2 (gigahertz) GHz.
In a Wan & Brennan approach, there are N sub-divider cells. Each cell divides the clock either by two (2) or three (3), which is determined by an output of a value stored in a memory, e.g., a read-only memory (ROM). This output is then updated at the rising edge of the output clock from the sub-divider cell. This approach provides a divider number ranging from 3N to 2N, wherein N is an integer, and can be used for high speed operation. However, this approach requires a ROM for each sub-divider cell and mapping control logic to control the output sequence of the ROM. This approach is complicated and also consumes a large layout area in comparison with other elements on the semiconductor chip.